A CMOS imager circuit includes a focal plane array of pixel cells, each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion region, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion region. The imager may also include a transistor for transferring charge from the photosensor to the floating diffusion region and another transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell, for example a four transistor pixel, perform the necessary functions of (1) photon to charge conversion; (2) transfer of charge to the floating diffusion node; (3) resetting the floating diffusion node to a known state before the transfer of charge to it; (4) selection of a pixel cell for readout; and (5) output and amplification of a signal representing a reset voltage and a pixel signal voltage based on the photo converted charges. The charge at the floating diffusion node is converted to a pixel output voltage by a source follower output transistor.
FIG. 1 illustrates a block diagram of a CMOS imager device 108 having a pixel array 100 with each pixel cell being constructed as described above. Pixel array 100 comprises a plurality of pixels arranged in a predetermined number of columns and rows (not shown). The pixels of each row in array 100 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 100. The row lines are selectively activated by the row driver 145 in response to row address decoder 155 and the column select lines are selectively activated by the column driver 160 in response to column address decoder 170. Thus, a row and column address is provided for each pixel.
The CMOS imager 108 is operated by the control circuit 150, which controls address decoders 155, 170 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 145, 160 that apply driving voltage to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal Vrst and a pixel image signal Vsig for each pixel are read by sample and hold circuitry 161 associated with the column driver 160. A differential signal Vrst-Vsig is produced and amplified by amplifier 162 and digitized by analog-to-digital converter 175. The analog-to-digital converter 175 converts the analog pixel signals to digital signals, which are fed to an image processor 180 to form and output a digital image.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
A schematic diagram of an exemplary CMOS three-transistor (3T) pixel cell 10 is illustrated in FIG. 2a. The three transistors include a reset transistor 32, a source follower transistor 34, and a row select transistor 36. A photosensor 26 converts incident light into charge. A floating diffusion region 28 receives charge from the photosensor 26 and is connected to the reset transistor 32 and the gate of the source follower transistor 34. The source follower transistor 34 outputs a signal proportional to the charge accumulated in the floating diffusion region 28 to a sampling circuit when the row select transistor 36 is turned on. The reset transistor 32 resets the floating diffusion region 28 to a known potential prior to transfer of charge from the photosensor 26. The photosensor 26 may be a photodiode, a photogate, or a photoconductor. If a photodiode is employed, the photodiode may be formed below a surface of the substrate and may be a buried p-n-p photodiode, buried n-p-n photodiode, buried p-n photodiode, or buried n-p photodiode, among others.
A schematic diagram of an exemplary CMOS four-transistor (4T) pixel cell 20 is illustrated in FIG. 3a. The four transistors include a transfer gate 30, a reset transistor 32, a source follower transistor 34, and a row select transistor 36. A photosensor 26 converts incident light into charge. A floating diffusion region 28 receives charge from the photosensor 26 through the transfer gate 30 (when activated) and is connected to the reset transistor 32 and the gate of the source follower transistor 34. The source follower transistor 34 outputs a signal proportional to the charge accumulated in the floating diffusion region 28 to a sampling circuit when the row select transistor 36 is turned on. The reset transistor 32 resets the floating diffusion region 28 to a known potential prior to transfer of charge from the photosensor 26. Similar to the 3T pixel cell 10 of FIG. 2a, the illustrated photosensor 26 may be a photodiode, a photogate, or a photoconductor. If a photodiode is employed, the photodiode may be formed below a surface of the substrate and may be a buried p-n-p photodiode, buried n-p-n photodiode, a buried p-n photodiode, or a buried n-p photodiode, among others.
A capacitor may also be connected to the floating diffusion node in order to increase the storage capacity as shown in FIG. 4a. In FIG. 4a, the pixel 200 has a capacitor C connected to floating diffusion node 228, to receive charge from the photosensor 226. The remainder of the pixel 200 is similar to the 4T pixel illustrated in FIG. 3a. 
Image sensors, such as an image sensor employing the conventional pixel cells 10, 20, 200 of FIGS. 2a, 3a and 4a, as well as sensors employing other pixel cell architectures, have a characteristic light dynamic range. Light dynamic range refers to the range of incident light that can be accommodated by an image sensor in a single frame of pixel data. It is desirable to have an image sensor with a high light dynamic range to image scenes that generate high light dynamic range incident signals, such as indoor rooms with windows to the outside, outdoor scenes with mixed shadows and bright sunshine, night-time scenes combining artificial lighting and shadows, and many others.
The electrical dynamic range for an image sensor is commonly defined as the ratio of its largest non-saturating signal to the standard deviation of the noise under dark conditions. The electrical dynamic range is limited on an upper end by the charge saturation level of the sensor, and on a lower end by noise imposed limitations and/or quantization limits of the analog to digital converter used to produce the digital image. When the light dynamic range of an image sensor is too small to accommodate the variations in light intensities of the imaged scene, e.g. by having a low light saturation level, the full range of the image scene is not reproduced. The illumination-voltage profile of the conventional pixels 10, 20 is typically linear as shown in FIG. 7, which illustrates an illumination v. voltage graph of a prior art pixel cell. A pixel cell's maximum voltage Vout-max may be reached at a relatively low level of illumination Imax-1 which causes the pixel cell to be easily saturated, thus limiting the dynamic range of the pixel. The relationship between electrical dynamic range and light dynamic range is shown in FIGS. 7 and 8.
When the incident light captured and converted into a charge by the photosensor during an integration period is greater than the capacity of the photosensor, excess charge may overflow and be transferred to adjacent pixels. This undesirable phenomenon is known as blooming, or charge cross talk, and results in a bright spot in the output image.
Another problem of image sensors is that the reset gate adjacent to the photosensor in three-transistor (3T) pixels or the transfer gate adjacent to the photosensor in four-transistor (4T) pixels tend to leak, creating signal loss from the photosensor during the integration period. Independent of the dynamic range problem, a substantial effort is being made in the art of image sensors to reduce or eliminate off-state leakage of adjacent transistors to minimize signal loss.
Thus, there is a desire and need for a pixel cell having improved saturation response and lower potential for blooming while benefiting from the leaky property of transistors.